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CB2 overcloking

Started by arturbac, December 25, 2013, 05:50:12 am

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A20 overcloking should work with updating bus and interface clock.
DDR interface clock is PLL5, and can be updated max;
MBUS can be set at 400M or higher;
AXI can be set max 450, can be set 1/3 of CPU if CPU clock is +1200M;
AHB is max 250, can be set 1/2 of AXI or 1/2 of PPL6M , or 1/4 of PPL6M;
APB0 is max 150M, can be set 1/2  of AHB;
PLL3, PLL4, PLL7, PLL8 can set higer.
you need to modify the core code yourself, they locate at arch/arm/mach-sun7i/clock (cpu-freq) and arch/arm/plat-sunxi/*;